Publicaciones en las que colabora con Antonio González Colás (24)

2011

  1. Global productiveness propagation: A code optimization technique to speculatively prune useless narrow computations

    Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

2009

  1. AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures

    IEEE Transactions on Computers, Vol. 58, Núm. 6, pp. 770-783

2008

  1. Mitosis: A speculative multithreaded processor based on precomputation slices

    IEEE Transactions on Parallel and Distributed Systems, Vol. 19, Núm. 7, pp. 914-925

2007

  1. Virtual cluster scheduling through the scheduling graph

    International Symposium on Code Generation and Optimization, CGO 2007

2006

  1. Instruction scheduling for a clustered VLIW processor with a word-interleaved cache

    Concurrency and Computation: Practice and Experience

2005

  1. Distributed data cache designs for clustered VLIW processors

    IEEE Transactions on Computers, Vol. 54, Núm. 10, pp. 1227-1241

  2. Mitosis compiler: An infrastructure for speculative threading based on pre-computation slices

    Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

  3. Mitosis compiler: An infrastructure for speculative threading based on pre-computation slices

    ACM SIGPLAN Notices, Vol. 40, Núm. 6, pp. 269-279

  4. Variable-based multi-module data caches for clustered VLIW processors

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

2003

  1. Flexible compiler-managed L0 buffers for clustered VLIW processors

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache

    International Symposium on Code Generation and Optimization, CGO 2003

2002

  1. An interleaved cache clustered VLIW processor

    Proceedings of the International Conference on Supercomputing

  2. Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  3. Exploiting pseudo-schedules to guide data dependence graph partitioning

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

2001

  1. A unified modulo scheduling and register allocation technique for clustered processors

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

  2. Clustered modulo scheduling in a VLIW architecture with distributed cache

    Journal of Instruction-Level Parallelism, Vol. 3

  3. Graph-partitioning based instruction scheduling for clustered processors

    Proceedings of the Annual International Symposium on Microarchitecture

2000

  1. Analyzing data locality in numeric applications

    IEEE Micro, Vol. 20, Núm. 4, pp. 58-66

  2. Instruction scheduling for clustered VLIW architectures

    Proceedings of the International Symposium on System Synthesis

  3. Modulo scheduling for a fully-distributed clustered VLIW architecture

    Proceedings of the Annual International Symposium on Microarchitecture